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1 of 36 october 3, 2011 ? 2011 integrated device technology, inc. ? idt and the idt logo are registered trademarks of integrated device technology, inc. device overview the 89HPES16H16 is a member of the idt precise? family of pci express? switching solutions. the pes16h16 is a 16-lane, 16-port peripheral chip that performs pci express packet switching with a feature set optimized for high-performance applications such as servers, storage, and communications/network ing. it provides connectivity and switching functions between a pci express upstream port and up to fifteen downstream ports and supports switching between downstream ports. features high performance pci express switch ? sixteen maximum switch ports ? sixteen x1 ports ? sixteen 2.5 gbps embedded serdes ? supports pre-emphasis and receive equalization on per-port basis ? delivers 64 gbps (8 gbps) of aggregate switching capacity ? low-latency cut-through switch architecture ? support for max payload size up to 2048 bytes ? supports two virtual channels and eight traffic classes ? pci express base specification revision 1.1 compliant flexible architecture with nume rous configuration options ? port arbitration schemes utilizing round robin algorithms ? virtual channels arbitration based on priority ? automatic polarity inversion on all lanes ? supports locked transactions, allowing use with legacy soft- ware ? ability to load device configuration from serial eeprom ? ability to control device via smbus highly integrated solution ? requires no external components ? incorporates on-chip internal memory for packet buffering and queueing ? integrates sixteen 2.5 gbps embedded full duplex serdes, 8b/ 10b encoder/decoder (no separate transceivers needed) reliability, availability, and serviceability (ras) features ? redundant upstream port failover capability ? supports optional pci express end-to-end crc checking ? internal end-to-end parity protection on all tlps ensures data integrity even in systems that do not implement end-to-end crc (ecrc) ? supports optional pci express advanced error reporting block diagram figure 1 internal block diagram 16 pci express lanes 16 x1 ports 16-port switch core frame buffer route table port arbitration scheduler dl/transaction layer serdes x1 dl/transaction layer serdes x1 dl/transaction layer serdes x1 dl/transaction layer serdes x1 . . . . . . . 89HPES16H16 data sheet 16-lane 16-port pci express? switch
2 of 36 october 3, 2011 idt 89HPES16H16 data sheet ? supports pci express hot-plug ? compatible with hot-plug i/o expanders used on pc motherboards ? supports hot-swap power management ? supports pci power management interface specification, revision 1.1 (pci-pm) ? supports powerdown modes at the link level (l0, l0s, l1, l2/l3 ready and l3) and at the device level (d0, d3 hot ) ? unused serdes disabled testability and debug features ? built in serdes pseudo-random bit stream (prbs) generator ? ability to read and write any internal register via the smbus ? ability to bypass link training and force any link into any mode ? provides statistics and performance counters thirty-two general purpose input/output pins ? each pin may be individually configured as an input or output ? each pin may be individually configured as an interrupt input ? some pins have selectable alternate functions packaged in a 23mm x 23mm 484- ball flip chip bga with 1mm ball spacing product description utilizing standard pci express interconnect, the pes16h16 provides the most efficient i/o connectivi ty for applications requiring high throughput, low latency, and simple board layout with a minimum number of board layers. it provides 64 gbps of aggregated, full-duplex switching capacity through 16 integrated serial lanes, using proven and robust idt technology. each lane provides 2.5 gbps of bandwidth in both directions and is fully compliant with pci express base specifica- tion 1.1. the pes16h16 is based on a flexible and efficient layered architec- ture. the pci express layer consists of serdes, physical, data link and transaction layers. the pes16h16 can operate either as a store and forward switch or a cut-through switch and is designed to switch memory and i/o transactions. it supports eight traffic classes (tcs) and two virtual channels (vcs) with sophisticated resource management to enable efficient switching and i/o connectivity. smbus interface the pes16h16 contains two smbus interfaces. the slave interface provides full access to the configuration registers in the pes16h16, allowing every configuration register in the device to be read or written by an external agent. the master interface allows the default configura- tion register values of the pes16h 16 to be overridden following a reset with values programmed in an external serial eeprom. the master interface is also used by an external hot-plug i/o expander. six pins make up each of the two smbus interfaces. these pins consist of an smbus clock pin, an smbus data pin, and 4 smbus address pins. in the slave interface, these address pins allow the smbus address to which the device responds to be configured. in the master interface, these address pins allow the smbus address of the serial configuration eeprom from which data is loaded to be config- ured. the smbus address is set up on negation of perstn by sampling the corresponding address pins. when the pins are sampled, the resulting address is assigned as shown in table 1. as shown in figure 3, the master and slave smbuses may be used in a unified or split configuration. in the unified configuration, shown in figure 3(a), the master and slave smbuses are tied together and the pes16h16 acts both as a smbus master as well as a smbus slave on this bus. this requires that the smbus master or processor that has access to pes16h16 registers supports smbus arbitration. in some systems, this smbus master interface may be implemented using general purpose i/o pins on a processor or micro controller, and may not support smbus arbitration. to support these systems, the pes16h16 may be configured to operate in a split configuration as shown in figure 3(b). in the split configuration, the master and slave smbuses operate as two independent buses and thus multi-master arbitration is never required. the pes16h16 supports reading and writing of the serial eeprom on the master smbus via the slave smbus, allowing in system programming of the serial eeprom. bit slave smbus address master smbus address 1 ssmbaddr[1] msmbaddr[1] 2 ssmbaddr[2] msmbaddr[2] 3 ssmbaddr[3] msmbaddr[3] 4 0 msmbaddr[4] 5 ssmbaddr[5] 1 61 0 71 1 table 1 master and slave smbus address assignment
3 of 36 october 3, 2011 idt 89HPES16H16 data sheet figure 3 smbus interface configuration examples hot-plug interface the pes16h16 supports pci express hot-plug on each downstream port (ports 1 through 15). to reduce the number of pins required on the device, the pes16h16 utilizes an external i/o expander, such as t hat used on pc motherboards, connected to the smbus master int erface. following reset and configuration, whenever the state of a hot-plug output needs to be modified, the pes16h16 generates an smbus transact ion to the i/o expander with the new value of all of the outputs. whenever a hot-plug input changes, the i/o expander generates an interrupt w hich is received on the ioexpintn input pin (alternate function of gpio) of the pe s16h16. in response to an i/o expander interrupt, the pes16h16 ge nerates an smbus transaction to read the state of all of the hot-plug inputs from the i/o expander. general purpose input/output the pes16h16 provides 32 general purpose i/o (gpio) pins t hat may be individually configur ed as general purpose inputs, general purpose outputs, or alternate functions. some gpio pins are shared wi th other on-chip functions. these alternate functions may be enabl ed via software, smbus slave interface, or serial configuration eeprom. pin description the following tables lists the functions of the pins provided on the pes16h16. some of the functions listed may be multiplexed onto the same pin. the active polarity of a signal is defined using a suffix. si gnals ending with an ?n? are defined as being active, or asserted, when at a logic zero (low) level. all other signals (including clocks, buses, and select lines ) will be interpreted as being active, or asserted, when at a logic one (high) level. differ- ential signals end with a suffix ?n? or ?p.? the differential signal ending in ?p? is the positive portion of the differential pair and the differential signal ending in ?n? is the negative porti on of the differential pair. signal type name/description pe0rp[0] pe0rn[0] i pci express port 0 serial data receive. differential pci express receive pair for port 0. port 0 is the upstream port. pe0tp[0] pe0tn[0] o pci express port 0 serial data transmit. differential pci express transmit pair for port 0. port 0 is the upstream port. pe1rp[0] pe1rn[0] i pci express port 1 serial data receive. differential pci express receive pair for port 1. pe1tp[0] pe1tn[0] o pci express port 1 serial data transmit. differential pci express transmit pair for port 1. pe2rp[0] pe2rn[0] i pci express port 2 serial data receive. differential pci express receive pair for port 2. pe2tp[0] pe2tn[0] o pci express port 2 serial data transmit. differential pci express transmit pair for port 2. table 2 pci express interface pins (part 1 of 3) processor pes16h16 ssmbclk ssmbdat msmbclk msmbdat smbus master other smbus devices serial eeprom processor pes16h16 ssmbclk ssmbdat msmbclk msmbdat smbus master other smbus devices serial eeprom ... ... (a) unified configuration and management bus (b) split configuration and management buses
4 of 36 october 3, 2011 idt 89HPES16H16 data sheet pe3rp[0] pe3rn[0] i pci express port 3 serial data receive. differential pci express receive pair for port 3. pe3tp[0] pe3tn[0] o pci express port 3 serial data transmit. differential pci express transmit pair for port 3. pe4rp[0] pe4rn[0] i pci express port 4 serial data receive. differential pci express receive pair for port 4. pe4tp[0] pe4tn[0] o pci express port 4 serial data transmit. differential pci express transmit pair for port 4. pe5rp[0] pe5rn[0] i pci express port 5 serial data receive. differential pci express receive pair for port 5. pe5tp[0] pe5tn[0] o pci express port 5 serial data transmit. differential pci express transmit pair for port 5. pe6rp[0] pe6rn[0] i pci express port 6 serial data receive. differential pci express receive pair for port 6. pe6tp[0] pe6tn[0] o pci express port 6 serial data transmit. differential pci express transmit pair for port 6. pe7rp[0] pe7rn[0] i pci express port 7 serial data receive. differential pci express receive pair for port 7. pe7tp[0] pe7tn[0] o pci express port 7 serial data transmit. differential pci express transmit pair for port 7. pe8rp[0] pe8rn[0] i pci express port 8 serial data receive. differential pci express receive pair for port 8. pe8tp[0] pe8tn[0] o pci express port 8 serial data transmit. differential pci express transmit pair for port 8. pe9rp[0] pe9rn[0] i pci express port 9 serial data receive. differential pci express receive pair for port 9. pe9tp[[0] pe9tn[0] o pci express port 9 serial data transmit. differential pci express transmit pair for port 9. pe10rp[0] pe10rn[0] i pci express port 10 serial data receive. differential pci express receive pair for port 10. pe10tp[0] pe10tn[0] o pci express port 10 serial data transmit. differential pci express transmit pair for port 10. pe11rp[0] pe11rn[0] i pci express port 11 serial data receive. differential pci express receive pair for port 11. pe11tp[0] pe11tn[0] o pci express port 11 serial data transmit. differential pci express transmit pair for port 11. pe12rp[0] pe12rn[0] i pci express port 12 serial data receive. differential pci express receive pair for port 12. pe12tp[0] pe12tn[0] o pci express port 12 serial data transmit. differential pci express transmit pair for port 12. pe13rp[0] pe13rn[0] i pci express port 13 serial data receive. differential pci express receive pair for port 13. pe13tp[0] pe13tn[0] o pci express port 13 serial data transmit. differential pci express transmit pair for port 13. w signal type name/description table 2 pci express interface pins (part 2 of 3)
5 of 36 october 3, 2011 idt 89HPES16H16 data sheet pe14rp[0] pe14rn[0] i pci express port 14 serial data receive. differential pci express receive pair for port 14. pe14tp[0] pe14tn[0] o pci express port 14 serial data transmit. differential pci express transmit pair for port 14. pe15rp[0] pe15rn[0] i pci express port 15 serial data receive. differential pci express receive pair for port 15. pe15tp[0] pe15tn[0] o pci express port 15 serial data transmit. differential pci express transmit pair for port 15. refclkm i pci express reference clock mode select. this signal selects the frequency of the reference clock input. 0x0 - 100 mhz 0x1 - 125 mhz perefclkp[3:0] perefclkn[3:0] i pci express reference clock. differential reference clock pair input. this clock is used as the reference clock by on-chip plls to generate the clocks required for the system logic and on-chip serdes. the frequency of the differential reference clock is determined by the refclkm signal. signal type name/description msmbaddr[4:1] i master smbus address. these pins determine the smbus address of the serial eeprom from which configuration information is loaded. msmbclk i/o master smbus clock. this bidirectional signal is used to synchronize transfers on the master smbus. it is active and generating the clock only when the eeprom or i/o expanders are being accessed. msmbdat i/o master smbus data. this bidirectional signal is used for data on the master smbus. ssmbaddr[5,3:1] i slave smbus address. these pins determine the smbus address to which the slave smbus interface responds. ssmbclk i/o slave smbus clock. this bidirectional signal is used to synchronize transfers on the slave smbus. ssmbdat i/o slave smbus data. this bidirectional signal is used for data on the slave smbus. table 3 smbus interface pins signal type name/description gpio[0] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. gpio[1] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. gpio[2] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. gpio[3] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. table 4 general purpose i/o pins (part 1 of 4) signal type name/description table 2 pci express interface pins (part 3 of 3)
6 of 36 october 3, 2011 idt 89HPES16H16 data sheet gpio[4] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. gpio[5] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: gpen alternate function pin type: output alternate function: general purpose event (gpe) output gpio[6] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: p1rstn alternate function pin type: output alternate function: reset output for downstream port 1 gpio[7] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: p2rstn alternate function pin type: output alternate function: reset output for downstream port 2 gpio[8] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: p3rstn alternate function pin type: output alternate function: reset output for downstream port 3 gpio[9] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: p4rstn alternate function pin type: output alternate function: reset output for downstream port 4 gpio[10] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: p5rstn alternate function pin type: output alternate function: reset output for downstream port 5 gpio[11] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: p6rstn alternate function pin type: output alternate function: reset output for downstream port 6 gpio[12] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: p7rstn alternate function pin type: output alternate function: reset output for downstream port 7 gpio[13] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: p8rstn alternate function pin type: output alternate function: reset output for downstream port 8 signal type name/description table 4 general purpose i/o pins (part 2 of 4)
7 of 36 october 3, 2011 idt 89HPES16H16 data sheet gpio[14] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: p9rstn alternate function pin type: output alternate function: reset output for downstream port 9 gpio[15] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: p10rstn alternate function pin type: output alternate function: reset output for downstream port 10 gpio[16] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: p11rstn alternate function pin type: output alternate function: reset output for downstream port 11 gpio[17] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: p12rstn alternate function pin type: output alternate function: reset output for downstream port 12 gpio[18] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: p13rstn alternate function pin type: output alternate function: reset output for downstream port 13 gpio[19] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: p14rstn alternate function pin type: output alternate function: reset output for downstream port 14 gpio[20] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: p15rstn alternate function pin type: output alternate function: reset output for downstream port 15 gpio[21] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: ioexpintn0 alternate function pin type: input alternate function: smbus i/o expander interrupt 0 gpio[22] 1 i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: ioexpintn1 alternate function pin type: input alternate function: smbus i/o expander interrupt 1 gpio[23] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: ioexpintn2 alternate function pin type: input alternate function: smbus i/o expander interrupt 2 signal type name/description table 4 general purpose i/o pins (part 3 of 4)
8 of 36 october 3, 2011 idt 89HPES16H16 data sheet gpio[24] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: ioexpintn3 alternate function pin type: input alternate function: smbus i/o expander interrupt 3 gpio[25] 1 i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: ioexpintn4 alternate function pin type: input alternate function: smbus i/o expander interrupt 4 gpio[26] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: ioexpintn5 alternate function pin type: input alternate function: smbus i/o expander interrupt 5 gpio[27] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: ioexpintn6 alternate function pin type: input alternate function: smbus i/o expander interrupt 6 gpio[28] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: ioexpintn7 alternate function pin type: input alternate function: smbus i/o expander interrupt 7 gpio[29] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. gpio[30] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. gpio[31] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pi n name: ioexpintn10 alternate function pin type: input alternate function: smbus i/o expander interrupt 10 1. gpio pins 22 and 25 are not available in the 23x23mm package. signal type name/description cclkds i common clock downstream. when the cclkds pin is asserted, it indicates that a common clock is being used between the downstream device and the downstream port. cclkus i common clock upstream. when the cclkus pin is asserted, it indicates that a common clock is being used between the upstream device and the upstream port. msmbsmode i master smbus slow mode. the assertion of this pin indicates that the master smbus should operate at 100 khz instead of 400 khz. this value may not be overridden. table 5 system pins (part 1 of 2) signal type name/description table 4 general purpose i/o pins (part 4 of 4)
9 of 36 october 3, 2011 idt 89HPES16H16 data sheet perstn i fundamental reset. assertion of this signal resets all logic inside the pes16h16 and initiates a pci express fundamental reset. rsthalt i reset halt. when this signal is asserted during a pci express fundamental reset, the pes16h16 executes the reset procedure and remains in a reset state with the master and slave smbuses active. this allows software to read and write registers internal to the device before normal device operation begins. the device exits the reset state when the rsthalt bit is cleared in the pa_swctl register by an smbus master. swmode[3:0] i switch mode. these configuration pins determine the pes16h16 switch operating mode. these pins should be static and not change following the negation of perstn. 0x0 - normal switch mode 0x1 - normal switch mode with serial eeprom initialization 0x2 through 0x7 - reserved 0x8 - normal switch mode with upstream port failover (port 0 selected as the upstream port) 0x9 - normal switch mode with upstream port failover (port 2 selected as the upstream port) 0xa - normal switch mode with serial eeprom initialization and upstream port failover (port 0 selected as the upstream port) 0xb - normal switch mode with serial eeprom initialization and upstream port failover (port 2 selected as the upstream port) 0xc through 0xf - reserved signal type name/description jtag_tck i jtag clock . this is an input test clock used to clock the shifting of data into or out of the boundary scan logic or jtag controller. jtag_tck is independent of the system clock with a nominal 50% duty cycle. jtag_tdi i jtag data input . this is the serial data input to the boundary scan logic or jtag controller. jtag_tdo o jtag data output . this is the serial data shifted out from the boundary scan logic or jtag controller. when no data is being shifted out, this signal is tri-stated. jtag_tms i jtag mode . the value on this signal controls the test mode select of the boundary scan logic or jtag controller. jtag_trst_n i jtag reset . this active low signal asynchronously resets the boundary scan logic and jtag tap controller. an external pull-up on the board is recommended to meet the jtag specification in cases where the tester can access this signal. however, for systems running in functional mode, one of the following should occur: 1) actively drive this signal low with control logic 2) statically drive this signal low with an external pull-down on the board table 6 test pins signal type name/description v dd core i core vdd. power supply for core logic. v dd i/o i i/o vdd. lvttl i/o buffer power supply. v dd pe i pci express digital power. pci express digital power used by the digital power of the serdes. table 7 power and ground pins signal type name/description table 5 system pins (part 2 of 2)
10 of 36 october 3, 2011 idt 89HPES16H16 data sheet v dd pea i pci express analog power. pci express analog power used by the pll and bias generator. v ss i ground. v tt pe pci express serial data transmit termination voltage. this pin allows the driver termination voltage to be set, enabling the system designer to control the common mode voltage and output voltage swing of the corresponding pci serial data transmit differential pair. signal type name/description table 7 power and ground pins
11 of 36 october 3, 2011 idt 89HPES16H16 data sheet pin characteristics note: some input pads of the pes16h16 do not contain internal pull- ups or pull-downs. unused inputs should be tied off to appropriate levels. this is especially critical for unused control signal i nputs which, if left floating, could adversely affect operation. also, any input pin left floating can cause a slight in crease in power consumption. function pin name type buffer i/o type internal resistor notes pci express interface pe0rn[0] i cml serial link pe0rp[0] i pe0tn[0] o pe0tp[0] o pe1rn[0] i pe1rp[0] i pe1tn[0] o pe1tp[0] o pe2rn[0] i pe2rp[0] i pe2tn[0] o pe2tp[0] o pe3rn[0] i pe3rp[0] i pe3tn[0] o pe3tp[0] o pe4rn[0] i pe4rp[0] i pe4tn[0] o pe4tp[0] o pe5rn[0] i pe5rp[0] i pe5tn[0] o pe5tp[0] o pe6rn[0] i pe6rp[0] i pe6tn[0] o pe6tp[0] o pe7rn[0] i pe7rp[0] i pe7tn[0] o pe7tp[0] o pe8rn[0] i table 8 pin characteristics (part 1 of 3)
12 of 36 october 3, 2011 idt 89HPES16H16 data sheet pci express interface (cont.) pe8rp[0] i cml serial link pe8tn[0] o pe8tp[0] o pe9rn[0] i pe9rp[0] i pe9tn[0] o pe9tp[0] o pe10rn[0] i pe10rp[0] i pe10tn[0] o pe10tp[0] o pe11rn[0] i pe11rp[0] i pe11tn[0] o pe11tp[0] o pe12rn[0] i pe12rp[0] i pe12tn[0] o pe12tp[0] o pe13rn[0] i pe13rp[0] i pe13tn[0] o pe13tp[0] o pe14rn[0] i pe14rp[0] i pe14tn[0] o pe14tp[0] o pe15rn[0] i pe15rp[0] i pe15tn[0] o pe15tp[0] o perefclkn[3:0] i lvpecl/ cml diff. clock input refer to table 9 perefclkp[3:0] i refclkm i lvttl input pull-down function pin name type buffer i/o type internal resistor notes table 8 pin characteristics (part 2 of 3)
13 of 36 october 3, 2011 idt 89HPES16H16 data sheet smbus msmbaddr[4:1] i lvttl pull-up msmbclk i/o sti 1 msmbdat i/o sti ssmbaddr[5,3:1] i pull-up ssmbclk i/o sti ssmbdat i/o sti general purpose i/o gpio[31:0] i/o lvttl pull-up system pins cclkds i lvttl input pull-up cclkus i pull-up msmbsmode i pull-down perstn i rsthalt i pull-down swmode[3:0] i pull-down ejtag / jtag jtag_tck i lvttl sti pull-up jtag_tdi i sti pull-up jtag_tdo o jtag_tms i sti pull-up jtag_trst_n i sti pull-up external pull-down 1. schmitt trigger input (sti) . function pin name type buffer i/o type internal resistor notes table 8 pin characteristics (part 3 of 3)
14 of 36 october 3, 2011 idt 89HPES16H16 data sheet logic diagram ? pes16h16 figure 4 pes16h16 logic diagram note: gpio pins 22 and 25 are not available in the 23x23mm package. ... reference clocks perefclkp[3:0] perefclkn[3:0] jtag_tck gpio[31:0] 32 general purpose i/o v dd core v dd i/o v dd pe v dd pea power/ground msmbaddr[4:1] msmbclk msmbdat 4 master smbus interface cclkus rsthalt system pins jtag_tdi jtag_tdo jtag_tms jtag_trst_n jtag pins v ss swmode[3:0] 4 4 4 cclkds perstn refclkm msmbsmode v tt pe pe0rp[0] pe0rn[0] pcie switch serdes input pe0tp[0] pe0tn[0] pcie switch serdes output port 0 port 0 pe1rp[0] pe1rn[0] pe1tp[0] pe1tn[0] pe2rp[0] pe2rn[0] pe2tp[0] pe2tn[0] pe3rp[0] pe3rn[0] pe3tp[0] pe3tn[0] pe15rp[0] pe15rn[0] pe15tp[0] pe15tn[0] pes16h16 ... ssmbaddr[5,3:1] ssmbclk ssmbdat 4 slave smbus interface pcie switch serdes output port 1 pcie switch serdes output port 2 pcie switch serdes output port 3 pcie switch serdes output port 15 pcie switch serdes input port 1 pcie switch serdes input port 2 pcie switch serdes input port 3 pcie switch serdes input port 15
15 of 36 october 3, 2011 idt 89HPES16H16 data sheet system clock parameters values based on systems running at recommended supply voltages and operating temperatures, as shown in tables 13 and 15. ac timing characteristics parameter description min typical max unit perefclk refclk freq input reference clock frequency range 100 125 1 1. the input clock frequency will be either 100 or 125 mhz depending on signal refclkm. mhz refclk dc 2 2. clkin must be ac coupled. use 0.01 ? 0.1 f ceramic capacitors. duty cycle of input clock 40 50 60 % t r , t f rise/fall time of input clocks 0.2*rcui rcui 3 3. rcui (reference clock unit interval) refers to the reference clock period. v sw differential input voltage swing 4 4. ac coupling required. 0.6 1.6 v t jitter input clock jitter (cycle-to-cycle) 125 ps r t termination resistor 110 ohms table 9 input clock requirements parameter description min 1 1. minimum, typical, and maximum values meet the requirements under pci specification 1.1 typical 1 max 1 units pcie transmit ui unit interval 399.88 400 400.12 ps t tx-eye minimum tx eye width 0.7 .9 ui t tx-eye-median-to- max-jitter maximum time between the jitter median and maximum deviation from the median 0.15 ui t tx-rise , t tx-fall d+ / d- tx output rise/fall time 50 90 ps t tx- idle-min minimum time in idle 50 ui t tx-idle-set-to- idle maximum time to transition to a valid idle after sending an idle ordered set 20 ui t tx-idle-to-diff- data maximum time to transition from valid idle to diff data 20 ui t tx-skew transmitter data skew between any 2 lanes 500 1300 ps pcie receive ui unit interval 399.88 400 400.12 ps t rx-eye (with jitter) minimum receiver eye width (jitter tolerance) 0.4 ui t rx-eye-medium to max jitter max time between jitter median & max deviation 0.3 ui t rx-idle-det-diff- enter time unexpected idle enter detect threshold integration time 10 ms t rx-skew lane to lane input skew 20 ns table 10 pcie ac timing characteristics
16 of 36 october 3, 2011 idt 89HPES16H16 data sheet figure 5 gpio ac timing waveform signal symbol reference edge min max unit timing diagram reference gpio gpio[31:0] 1 1. gpio signals must meet the setup and hold times if they are synchronous or the minimum pulse width if they are asynchronous. tpw_13b 2 2. the values for this symbol were determined by calculation, not by testing. none 50 ? ns see figure 5. table 11 gpio ac timing characteristics signal symbol reference edge min max unit timing diagram referenc e jtag jtag_tck tper_16a none 50.0 ? ns see figure 6. thigh_16a, tlow_16a 10.0 25.0 ns jtag_tms 1 , jtag_tdi 1. the jtag specification, ieee 1149.1, recommends that jtag_tms should be held at 1 while the signal applied at jtag_trst_n changes from 0 to 1. otherwise, a race may occur if jtag_trst_n is deasserted (going from low to high) on a rising edge of jtag _tck when jtag_tms is low, because the tap controller might go to either the run-test/idle state or stay in the test-logic-reset sta te. tsu_16b jtag_tck rising 2.4 ? ns thld_16b 1.0 ? ns jtag_tdo tdo_16c jtag_tck falling ? 20 ns tdz_16c 2 2. the values for this symbol were determined by calculation, not by testing. ?20ns jtag_trst_n tpw_16d 2 none 25.0 ? ns table 12 jtag ac timing characteristics tpw_13b extclk gpio (asynchronous input)
17 of 36 october 3, 2011 idt 89HPES16H16 data sheet figure 6 jtag ac timing waveform recommended operating supply voltages absolute maximum voltage rating warning: for proper and reliable operation in adherence with this data s heet, the device should not exceed the recommended operating vol tages in table 13. the absolute maximum operating voltages in table 14 are offered to provide guidelines for voltage excursions outsi de the recommended voltage ranges. device functionality is not guaranteed at these c onditions and sustained operation at these values or any expos ure to voltages outside the maximum range may adversely affect device functionality and reliability. symbol parameter minimum typical maximum unit v dd core internal logic supply 0.9 1.0 1.1 v v dd i/o i/o supply except for serdes lvpecl/cml 3.0 3.3 3.6 v v dd pe pci express digital power 0.9 1.0 1.1 v v dd pea pci express analog power 0.9 1.0 1.1 v v tt pe pci express serial data transmit termination voltage 1.425 1.5 1.575 v v ss common ground 0 0 0 v table 13 pes16h16 operating voltages v dd core v dd pe v dd ape v tt pe v dd i/o 1.5v 1.5v 1.5v 2.5v 5.0v table 14 pes16h16 absolute maximum voltage rating tpw_16d tdz_16c tdo_16c thld_16b tsu_16b thld_16b tsu_16b tlow_16a tlow_16a tper_16a thigh_16a jtag_tck jtag_tdi jtag_tms jtag_tdo jtag_trst_n
18 of 36 october 3, 2011 idt 89HPES16H16 data sheet power-up sequence this section describes the sequence in which various voltages must be applied to the part during power-up to ensure proper func tionality. for the pes16h16, the power-up sequence must be as follows: 1. v dd i/o ? 3.3v 2. v dd core, v dd pe, v dd pea ? 1.0v 3. v tt pe ? 1.5v when powering up, each voltage level must ramp and stabilize prio r to applying the next voltage in the sequence to ensure inter nal latch-up issues are avoided. there are no maximum time limitations in ramping to valid power levels. the power-down sequence must be in the rev erse order of the power-up sequence. recommended operating temperature power consumption typical power is measured under the following conditions: 25c ambient, 35% total link usage on all ports, typical voltages def ined in table 13 (and also listed below). maximum power is measured under the following conditions: 70c ambient, 85% total link usage on all ports, maximum voltages def ined in table 13 (and also listed below). grade temperature commercial 0 c to +70 c ambient industrial -40 c to +85 c ambient table 15 pes16h16 operating temperatures number of active lanes per port core supply pcie digital supply pcie analog supply pcie termin- ation supply i/o supply total typ 1.0v max 1.1v typ 1.0v max 1.1v typ 1.0v max 1.1v typ 1.5v max 1.575v typ 3.3v max 3.6v typ power max power sixteen x1 ma 2320 2880 723 867.5 1157 1500 370.5 500 5 5 watts 2.32 3.17 0.72 0.95 1.16 1.65 0.56 0.79 0.017 0.018 4.77 6.58 table 16 pes16h16 power consumption
19 of 36 october 3, 2011 idt 89HPES16H16 data sheet thermal considerations this section describes thermal cons iderations for the pes16h16 (23mm 2 fcbga484 package). the data in table 17 below contains information that is relevant to the thermal performance of the pes16h16 switch. note: the parameter ja(eff) is not the absolute thermal resistance for the package as defined by jedec (jesd-51). because resistance can vary with the number of board layers, size of the board, and airflow, ja(eff) is the effective thermal resistance. the values for effective ja given above are based on a 10-layer, standard height, full length (4.3?x12.2?) pcie add-in card. symbol parameter value units conditions t j(max) junction temperature 125 o c maximum t a(max) ambient temperature 70 o c maximum for commercial-rated products ja(effective) effective thermal resistance, junction-to-ambient 13.4 o c/w zero air flow 7.2 o c/w 1 m/s air flow 6.2 o c/w 2 m/s air flow jb thermal resistance, junction-to-board 2.5 o c/w jc thermal resistance, junction-to-case 0.1 o c/w p power dissipation of the device 6.58 watts maximum table 17 thermal specifications for pes16h16, 23x23mm fcbga484 package
20 of 36 october 3, 2011 idt 89HPES16H16 data sheet dc electrical characteristics values based on systems running at recommended supply voltages, as shown in table 13. note: see table 8, pin characteristics, for a complete i/o listing. i/o type parameter description min 1 typ 1 max 1 unit conditions serial link pcie transmit v tx-diffp-p differential peak-to-peak output voltage 800 1200 mv v tx-de-ratio de-emphasized differential output voltage -3 -4 db v tx-dc-cm dc common mode voltage -0.1 1 3.7 v v tx-cm-acp rms ac peak common mode output volt- age 20 mv v tx-cm-dc- active-idle-delta abs delta of dc common mode voltage between l0 and idle 100 mv v tx-cm-dc-line- delta abs delta of dc common mode voltage between d+ and d- 25 mv v tx-idle-diffp electrical idle diff peak output 20 mv v tx-rcv-detect voltage change during receiver detection 600 mv rl tx-diff transmitter differential return loss 12 db rl tx-cm transmitter common mode return loss 6 db z tx-deff-dc dc differential tx impedance 80 100 120 z ose single ended tx impedance 40 50 60 transmitter eye diagram tx eye height (de-emphasized bits) 505 650 mv transmitter eye diagram tx eye height (transition bits) 800 950 mv pcie receive v rx-diffp-p differential input voltage (peak-to-peak) 175 1200 mv v rx-cm-ac receiver common-mode voltage for ac coupling 150 mv rl rx-diff receiver differential return loss 15 db rl rx-cm receiver common mode return loss 6 db z rx-diff-dc differential input impedance (dc) 80 100 120 z rx-comm-dc single-ended input impedance 40 50 60 z rx-comm-high- z-dc powered down input common mode impedance (dc) 200k 350k v rx-idle-det- diffp-p electrical idle detect threshold 65 175 mv pcie refclk c in input capacitance 1.5 ? pf table 18 dc electrical characteristics (part 1 of 2)
21 of 36 october 3, 2011 idt 89HPES16H16 data sheet other i/os low drive output i ol ?2.5?ma v ol = 0.4v i oh ?-5.5?ma v oh = 1.5v high drive output i ol ? 12.0 ? ma v ol = 0.4v i oh ?-20.0?ma v oh = 1.5v schmitt trig- ger input (sti) v il -0.3 ? 0.8 v ? v ih 2.0 ? v dd i/o + 0.5 v? input v il -0.3 ? 0.8 v ? v ih 2.0 ? v dd i/o + 0.5 v? capacitance c in ??8.5pf ? leakage inputs ? ? + 10 av dd i/o (max) i/o leak w / o pull-ups/downs ??+ 10 av dd i/o (max) i/o leak with pull-ups/downs ??+ 80 av dd i/o (max) 1. minimum, typical, and maximum values meet the requirements under pci specification 1.0a. i/o type parameter description min 1 typ 1 max 1 unit conditions table 18 dc electrical characteristics (part 2 of 2)
22 of 36 october 3, 2011 idt 89HPES16H16 data sheet option a package ? 484-bga signal pinout for pes16h16 the following table lists the pin numbers and signal names for the pes16h16 device. pin function alt pin function alt pin function alt pin function alt a1 v dd i/o b13 v ss d3 gpio_27 e15 v ss a2 gpio_16 b14 nc d4 gpio_23 e16 v dd pe a3 v ss b15 nc d5 gpio_20 e17 v dd pe a4 pe9tn00 b16 v ss d6 v ss e18 jtag_trst_n a5 pe8tn00 b17 nc d7 pe9rp00 e19 ssmbclk a6 v ss b18 pe2tn00 d8 pe9rn00 e20 ssmbaddr_2 a7 pe3rp00 b19 msmbaddr_3 d9 pe8rp00 e21 pe1tp00 a8 nc b20 jtag_tdo d10 pe8rn00 e22 pe1tn00 a9 v ss b21 perstn d11 v ss f1 pe10rp00 a10 perefclkn1 b22 jtag_tdi d12 nc f2 pe10rn00 a11 v ss c1 v dd i/o d13 nc f3 v ss a12 pe3tn00 c2 gpio_21 d14 nc f4 gpio_30 a13 v ss c3 gpio_19 d15 nc f5 v dd i/o a14 nc c4 v ss d16 pe2rp00 f6 v dd i/o a15 nc c5 v ss d17 pe2rn00 f7 v dd pe a16 v ss c6 v ss d18 msmbaddr_1 f8 v dd pe a17 nc c7 v ss d19 v dd i/o f9 v dd pe a18 pe2tp00 c8 v ss d20 cclkds f10 v dd core a19 msmbsmode c9 v ss d21 ssmbaddr_1 f11 v dd core a20 msmbdat c10 v ss d22 ssmbaddr_3 f12 v dd core a21 jtag_tms c11 v ss e1 v ss f13 v dd core a22 v ss c12 v ss e2 v ss f14 v dd pe b1 v ss c13 v ss e3 gpio_31 f15 v dd pe b2 gpio_18 c14 v ss e4 gpio_28 f16 v dd i/o b3 v ss c15 v ss e5 gpio_26 f17 v dd i/o b4 pe9tp00 c16 v ss e6 gpio_17 f18 ssmbaddr_5 b5 pe8tp00 c17 v ss e7 v dd pe f19 v ss b6 v ss c18 msmbaddr_4 e8 v ss f20 v ss b7 pe3rn00 c19 msmbaddr_2 e9 v tt pe f21 nc b8 nc c20 msmbclk e10 v tt pe f22 nc b9 v ss c21 ssmbdat e11 v dd pea g1 pe11rp00 b10 perefclkp1 c22 jtag_tck e12 v dd pea g2 pe11rn00 b11 v ss d1 gpio_29 e13 v tt pe g3 v ss b12 pe3tp00 d2 gpio_24 e14 v tt pe g4 v ss table 19 pes16h16 signal pin-out (part 1 of 4)
23 of 36 october 3, 2011 idt 89HPES16H16 data sheet g5 v dd i/o h20 v ss k13 v ss m6 v ss g6 v dd pe h21 nc k14 v dd core m7 v ss g7 v ss h22 nc k15 v dd core m8 v dd core g8 v dd core j1 pe10tn00 k16 v ss m9 v dd core g9 v dd core j2 pe10tp00 k17 v dd pe m10 v ss g10 v ss j3 v ss k18 v tt pe m11 v dd core g11 v dd core j4 v ss k19 nc m12 v dd core g12 v dd core j5 v tt pe k20 v ss m13 v ss g13 v ss j6 v dd pe k21 v ss m14 v dd core g14 v dd core j7 v ss k22 v ss m15 v dd core g15 v dd core j8 v dd core l1 v ss m16 v ss g16 v ss j9 v dd core l2 v ss m17 v ss g17 v dd i/o j10 v ss l3 v ss m18 v dd pea g18 v ss j11 v dd core l4 v ss m19 nc g19 pe1rn00 j12 v dd core l5 v dd pea m20 v ss g20 v ss j13 v ss l6 v ss m21 v ss g21 v ss j14 v dd core l7 v ss m22 v ss g22 v ss j15 v dd core l8 v dd core n1 v ss h1 v ss j16 v ss l9 v dd core n2 v ss h2 v ss j17 v dd pe l10 v ss n3 v ss h3 v ss j18 v tt pe l11 v dd core n4 v ss h4 v ss j19 nc l12 v dd core n5 v tt pe h5 v dd pe j20 v ss l13 v ss n6 v ss h6 v dd pe j21 nc l14 v dd core n7 v ss h7 v ss j22 nc l15 v dd core n8 v dd core h8 v dd core k1 pe11tn00 l16 v ss n9 v dd core h9 v dd core k2 pe11tp00 l17 v ss n10 v ss h10 v ss k3 v ss l18 v dd pea n11 v dd core h11 v dd core k4 v ss l19 nc n12 v dd core h12 v dd core k5 v tt pe l20 v ss n13 v ss h13 v ss k6 v ss l21 pe0tp00 n14 v dd core h14 v dd core k7 v ss l22 pe0tn00 n15 v dd core h15 v dd core k8 v dd core m1 perefclkn2 n16 v ss h16 v ss k9 v dd core m2 perefclkp2 n17 v ss h17 v dd pe k10 v ss m3 v ss n18 v tt pe h18 v dd pe k11 v dd core m4 v ss n19 v ss h19 pe1rp00 k12 v dd core m5 v dd pea n20 v ss pin function alt pin function alt pin function alt pin function alt table 19 pes16h16 signal pin-out (part 2 of 4)
24 of 36 october 3, 2011 idt 89HPES16H16 data sheet n21 perefclkn0 r14 v dd core u7 v dd pe v22 pe15tp00 n22 perefclkp0 r15 v dd core u8 v dd pe w1 v ss p1 pe4tn00 r16 v ss u9 v dd pe w2 v ss p2 pe4tp00 r17 v dd pe u10 v dd core w3 v ss p3 v ss r18 v ss u11 v dd core w4 refclkm p4 v ss r19 pe15rn00 u12 v dd core w5 rsthalt p5 v tt pe r20 v ss u13 v dd core w6 swmode_1 p6 v dd pe r21 nc u14 v dd pe w7 v ss p7 v ss r22 nc u15 v dd pe w8 v ss p8 v dd core t1 v ss u16 v dd i/o w9 v ss p9 v dd core t2 v ss u17 v dd i/o w10 v ss p10 v ss t3 v ss u18 v ss w11 v dd pea p11 v dd core t4 v ss u19 pe14rn00 w12 v ss p12 v dd core t5 v ss u20 v ss w13 v ss p13 v ss t6 v dd pe u21 v ss w14 v ss p14 v dd core t7 v ss u22 v ss w15 v dd i/o p15 v dd core t8 v dd core v1 pe5rp00 w16 gpio_01 p16 v ss t9 v dd core v2 pe5rn00 w17 gpio_03 p17 v dd pe t10 v ss v3 v ss w18 gpio_04 p18 v tt pe t11 v dd core v4 v ss w19 gpio_08 p19 pe15rp00 t12 v dd core v5 v dd i/o w20 v ss p20 v ss t13 v ss v6 v dd i/o w21 pe14tn00 p21 v ss t14 v dd core v7 v ss w22 pe14tp00 p22 v ss t15 v dd core v8 v dd pe y1 v dd i/o r1 pe5tn00 t16 v ss v9 v tt pe y2 cclkus r2 pe5tp00 t17 v dd pe v10 v tt pe y3 v dd i/o r3 v ss t18 v dd pe v11 v dd pea y4 swmode_0 r4 v ss t19 pe14rp00 v12 v tt pe y5 v ss r5 v dd pe t20 v ss v13 v tt pe y6 v ss r6 v dd pe t21 pe0rn00 v14 v dd pe y7 v ss r7 v ss t22 pe0rp00 v15 v dd pe y8 v ss r8 v dd core u1 pe4rp00 v16 v dd i/o y9 v ss r9 v dd core u2 pe4rn00 v17 gpio_06 y10 v ss r10 v ss u3 v ss v18 gpio_11 y11 v ss r11 v dd core u4 v ss v19 v ss y12 v ss r12 v dd core u5 v ss v20 v ss y13 v ss r13 v ss u6 v dd i/o v21 pe15tn00 y14 v ss pin function alt pin function alt pin function alt pin function alt table 19 pes16h16 signal pin-out (part 3 of 4)
25 of 36 october 3, 2011 idt 89HPES16H16 data sheet alternate signal functions y15 v ss aa6 pe7rn00 aa19 gpio_05 ab10 v ss y16 v ss aa7 v ss aa20 v dd i/o ab11 perefclkn3 y17 v ss aa8 pe6tp00 aa21 gpio_12 ab12 v ss y18 gpio_00 aa9 pe7tp00 aa22 gpio_14 ab13 pe12tn00 y19 gpio_07 aa10 v ss ab1 v dd i/o ab14 pe13tn00 y20 gpio_09 aa11 perefclkp3 ab2 v ss ab15 v ss y21 v ss aa12 v ss ab3 swmode_02 ab16 pe12rp00 y22 v ss aa13 pe12tp00 ab4 v ss ab17 pe13rp00 aa1 v ss aa14 pe13tp00 ab5 pe6rp00 ab18 v ss aa2 v dd i/o aa15 v ss ab6 pe7rp00 ab19 gpio_02 aa3 swmode_3 aa16 pe12rn00 ab7 v ss ab20 gpio_10 aa4 v ss aa17 pe13rn00 ab8 pe6tn00 ab21 gpio_13 aa5 pe6rn00 aa18 v ss ab9 pe7tn00 ab22 gpio_15 pin gpio alternate pin gpio alternate aa19 gpio_05 gpen e6 gpio_17 p12rstn v17 gpio_06 p1rstn b2 gpio_18 p13rstn y19 gpio_07 p2rstn c3 gpio_19 p14rstn w19 gpio_08 p3rstn d5 gpio_20 p15rstn y20 gpio_09 p4rstn c2 gpio_21 ioexpintn0 ab20 gpio_10 p5rstn d4 gpio_23 ioexpintn2 v18 gpio_11 p6rstn d2 gpio_24 ioexpintn3 aa21 gpio_12 p7rstn e5 gpio_26 ioexpintn5 ab21 gpio_13 p8rstn d3 gpio_27 ioexpintn6 aa22 gpio_14 p9rstn e4 gpio_28 ioexpintn7 ab22 gpio_15 p10rstn e3 gpio_31 ioexpintn10 a2 gpio_16 p11rstn ? ? ? table 20 pes16h16 alternate signal functions pin function alt pin function alt pin function alt pin function alt table 19 pes16h16 signal pin-out (part 4 of 4)
26 of 36 october 3, 2011 idt 89HPES16H16 data sheet no connection pins power pins no connection a8 b15 f21 j22 a14 b17 f22 k19 a15 d12 h21 l19 a17 d13 h22 m19 b8 d14 j19 r21 b14 d15 j21 r22 table 21 pes16h16 no connection pins v dd core v dd core v dd core v dd io v dd pe v dd pe v dd pea v tt pe f10k9p8a1e7p6e11e9 f11 k11 p9 c1 e16 p17 e12 e10 f12 k12 p11 d19 e17 r5 l5 e13 f13 k14 p12 f5 f7 r6 l18 e14 g8 k15 p14 f6 f8 r17 m5 j5 g9 l8 p15 f16 f9 t6 m18 j18 g11 l9 r8 f17 f14 t17 v11 k5 g12 l11 r9 g5 f15 t18 w11 k18 g14 l12 r11 g17 g6 u7 n5 g15l14r12u6h5u8 n18 h8 l15 r14 u16 h6 u9 p5 h9 m8 r15 u17 h17 u14 p18 h11 m9 t8 v5 h18 u15 v9 h12 m11 t9 v6 j6 v8 v10 h14 m12 t11 v16 j17 v14 v12 h15 m14 t12 w15 k17 v15 v13 j8 m15 t14 y1 j9 n8 t15 y3 j11 n9 u10 aa2 j12 n11 u11 aa20 j14 n12 u12 ab01 j15 n14 u13 k8 n15 ? table 22 pes16h16 power pins
27 of 36 october 3, 2011 idt 89HPES16H16 data sheet ground pins v ss v ss v ss v ss v ss v ss v ss a3 c17 h16 l16 p4 u4 y10 a6 d6 h20 l17 p7 u5 y11 a9 d11 j3 l20 p10 u18 y12 a11 e1 j4 m3 p13 u20 y13 a13 e2 j7 m4 p16 u21 y14 a16 e8 j10 m6 p20 u22 y15 a22 e15 j13 m7 p21 v3 y16 b1 f3 j16 m10 p22 v4 y17 b3 f19 j20 m13 r3 v7 y21 b6 f20 k3 m16 r4 v19 y22 b9 g3 k4 m17 r7 v20 aa1 b11 g4 k6 m20 r10 w1 aa4 b13 g7 k7 m21 r13 w2 aa7 b16 g10 k10 m22 r16 w3 aa10 c4 g13 k13 n1 r18 w7 aa12 c5 g16 k16 n2 r20 w8 aa15 c6 g18 k20 n3 t1 w9 aa18 c7 g20 k21 n4 t2 w10 ab2 c8 g21 k22 n6 t3 w12 ab4 c9 g22 l1 n7 t4 w13 ab7 c10 h1 l2 n10 t5 w14 ab10 c11 h2 l3 n13 t7 w20 ab12 c12h3 l4n16t10y5ab15 c13h4 l6n17t13y6ab18 c14h7 l7n19t16y7 c15 h10 l10 n20 t20 y8 c16 h13 l13 p3 u3 y9 table 23 pes16h16 ground pins
28 of 36 october 3, 2011 idt 89HPES16H16 data sheet signals listed alphabetically signal name i/o type location signal category cclkds i d20 system cclkus i y2 gpio_00 i/o y18 general purpose input/output gpio_01 i/o w16 gpio_02 i/o ab19 gpio_03 i/o w17 gpio_04 i/o w18 gpio_05 i/o aa19 gpio_06 i/o v17 gpio_07 i/o y19 gpio_08 i/o w19 gpio_09 i/o y20 gpio_10 i/o ab20 gpio_11 i/o v18 gpio_12 i/o aa21 gpio_13 i/o ab21 gpio_14 i/o aa22 gpio_15 i/o ab22 gpio_16 i/o a2 gpio_17 i/o e6 gpio_18 i/o b2 gpio_19 i/o c3 gpio_20 i/o d5 gpio_21 i/o c2 gpio_23 i/o d4 gpio_24 i/o d2 gpio_26 i/o e5 gpio_27 i/o d3 gpio_28 i/o e4 gpio_29 i/o d1 gpio_30 i/o f4 gpio_31 i/o e3 table 24 89pes16h16 alphabetical signal list (part 1 of 4)
29 of 36 october 3, 2011 idt 89HPES16H16 data sheet jtag_tck i c22 jtag jtag_tdi i b22 jtag_tdo o b20 jtag_tms i a21 jtag_trst_n i e18 msmbaddr_1 i d18 smbus msmbaddr_2 i c19 msmbaddr_3 i b19 msmbaddr_4 i c18 msmbclk i/o c20 msmbdat i/o a20 msmbsmode i a19 system no connection see table 21 for a listing of no connection pins. pe0rn00 i t21 pci express pe0rp00 i t22 pe0tn00 o l22 pe0tp00 o l21 pe1rn00 i g19 pe1rp00 i h19 pe1tn00 o e22 pe1tp00 o e21 pe2rn00 i d17 pe2rp00 i d16 pe2tn00 o b18 pe2tp00 o a18 pe3rn00 i b7 pe3rp00 i a7 pe3tn00 o a12 pe3tp00 o b12 pe4rn00 i u2 pe4rp00 i u1 pe4tn00 o p1 pe4tp00 o p2 pe5rn00 i v2 pe5rp00 i v1 pe5tn00 o r1 signal name i/o type location signal category table 24 89pes16h16 alphabetical signal list (part 2 of 4)
30 of 36 october 3, 2011 idt 89HPES16H16 data sheet pe5tp00 o r2 pci express (cont.) pe6rn00 i aa5 pe6rp00 i ab5 pe6tn00 o ab8 pe6tp00 o aa8 pe7rn00 i aa6 pe7rp00 i ab6 pe7tn00 o ab9 pe7tp00 o aa9 pe8rn00 i d10 pe8rp00 i d9 pe8tn00 o a5 pe8tp00 o b5 pe9rn00 i d8 pe9rp00 i d7 pe9tn00 o a4 pe9tp00 o b4 pe10rn00 i f2 pe10rp00 i f1 pe10tn00 o j1 pe10tp00 o j2 pe11rn00 i g2 pe11rp00 i g1 pe11tn00 o k1 pe11tp00 o k2 pe12rn00 i aa16 pe12rp00 i ab16 pe12tn00 o ab13 pe12tp00 o aa13 pe13rn00 i aa17 pe13rp00 i ab17 pe13tn00 o ab14 pe13tp00 o aa14 pe14rn00 i u19 pe14rp00 i t19 pe14tn00 o w21 signal name i/o type location signal category table 24 89pes16h16 alphabetical signal list (part 3 of 4)
31 of 36 october 3, 2011 idt 89HPES16H16 data sheet pe14tp00 o w22 pci express (cont.) pe15rn00 i r19 pe15rp00 i p19 pe15tn00 o v21 pe15tp00 o v22 perefclkn0 i n21 perefclkn1 i a10 perefclkn2 i m1 perefclkn3 i ab11 perefclkp0 i n22 perefclkp1 i b10 perefclkp2 i m2 perefclkp3 i aa11 perstn i b21 system refclkm i w4 pci express rsthalt i w5 system ssmbaddr_1 i d21 smbus ssmbaddr_2 i e20 ssmbaddr_3 i d22 ssmbaddr_5 i f18 ssmbclk i/o e19 ssmbdat i/o c21 swmode_0 i y4 system swmode_1 i w6 swmode_2 i ab3 swmode_3 i aa3 v dd core, v dd- pea, v dd io, v dd pe , v tt pe see table 22 for a listing of power pins. v ss see table 23 for a listing of ground pins. signal name i/o type location signal category table 24 89pes16h16 alphabetical signal list (part 4 of 4)
32 of 36 october 3, 2011 idt 89HPES16H16 data sheet pes16h16 pinout ? top view 1 2 3 4 5 6 7 8 910111213141516 vss (ground) v dd core (power) v dd i/o (power) 17 18 19 20 21 22 v tt pe (power) v dd pe (power) v dd pea (power) signals a b c d e f g h j k l m n p r t u v w y aa ab x 1 2 3 4 5 6 7 8 9 10 1112 13141516 17 18 19 20 21 22 a b c d e f g h j k l m n p r t u v w y aa ab no connect x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
33 of 36 october 3, 2011 idt 89HPES16H16 data sheet pes16h16 package drawing ? 484-pin bl484/br484 www.idt.com t id
34 of 36 october 3, 2011 idt 89HPES16H16 data sheet pes16h16 package drawing ? page two www.idt.com t id
35 of 36 october 3, 2011 idt 89HPES16H16 data sheet revision history april 7, 2008 : publication of preliminary data sheet with 23x23mm fcbga package option. april 16, 2008 : in table 16, thermal specifications, revised values for ja , jb , and jc .. october 21, 2009 : added industrial temperature to ordering codes on page 35. october 3, 2011: added new table 14, pes16h16 absolute maximum voltage rating.
36 of 36 october 3, 2011 idt 89HPES16H16 data sheet corporate headquarters 6024 silver creek valley road san jose, ca 95138 for sales: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com for tech support: email: ssdhelp@idt.com phone: 408-284-8208 ? ordering information valid combinations 89HPES16H16zabl 484-ball fcbga package, commercial temperature 89HPES16H16zabr 484-ball rohs fcbga package, commercial temperature 89HPES16H16zabli 484-ball fcbga package, industrial temperature 89HPES16H16zabri 484-ball rohs fcbga package, industrial temperature nn aaaa nnann aa a operating voltage device family product package temp range h blank commercial temperature (0c to +70c ambient) product family 89 serial switching product 16h16 16-lane, 16-port 1.0v +/- 0.1v core voltage detail pci express switch pes legend a = alpha character n = numeric character aa device revision za za revision i industrial temperature (-40 c to +85 c ambient) 484-ball fcbga bl 484-ball fcbga, rohs br

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